View ISL6446A_6216666.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. dual (180out-of-phase) pwm and linear controller ISL6446A the ISL6446A is a high-performan ce, triple output controller that provides a single high-frequency power solution primarily for broadband, dsl and networking applications. this device integrates complete control, monitoring and protection functions for two synchronous buck pwm controllers and one linear controller. input voltage ripple and total rms input current is substantially reduced by synchronized 180 out-of-phase operation of the two pwms. the two pwm buck converters provide simple voltage mode control. the output voltage of the converters can be precisely regulated to as low as 0.6v, with a maximum tolerance of 1.5% over-temperature and line variations. programmable switching frequency down to 100khz provides optimized low cost solution for atx power supplie s. it is also able to operate up to 2.5mhz to deliver compact solutions. the linear controller provides a low-current output. each pwm controller has soft-start and independent enable functions combined on a single pin. a capacitor from ss/en to ground sets the soft-start time; pulling ss/en pin below 1v disables the controller. both outputs can soft-start into a pre-biased load. the ISL6446A incorporates robust protection features. an adjustable overcurrent protection circuit monitors the output current by sensing the voltage drop across the upper mosfet r ds(on) . latch-off mode overcurrent operation protects the dc/dc converters from damage under overload and short circuit conditions. a pgood signal is issued when soft-start is complete and pwm outputs are within 10% of their regulated values and the linear regulator outp ut is higher than 75% of its nominal value. thermal shut-down circuitry turns the device off if the ic temperature exceeds +150c. features ? 4.5v to 5.5v or 5.5v to 24v input voltage range ? three programmable power output voltages - two pwm controllers with out-of-phase operation - voltage-mode pwm control - one linear controller ? programmable switching frequency from 100khz to 2.5mhz ? fast transient response - high-bandwidth error amplifier ?extensive circuit pr otection functions - undervoltage, and over-temperature - overvoltage with latch-off mode - programmable overcurrent limit with latch-off mode - lossless current sensing (no sense resistor needed) ? externally adjustable soft-start time - independent enable control - voltage tracking capability - able to soft-start into a pre-biased load ? pgood output with delay applications ? atx power supplies ? dsp, asic, and fpga point of load regulation ? industrial and security networking applications figure 1. typical application figure 2. efficiency vs lo ad current (obtained from ISL6446Aeval1z) comp1 fb1 comp2 fb2 pgood rt ss/en1 sgnd pgnd lcfb lcdr lgate2 phase2 ugate2 boot2 ocset2 lgate1 phase1 ugate1 boot1 ocset1 vin vcc ss/en2 feedback and compensation network feedback and compensation network vout1 vout2 r1 r2 c vcc vout1 c out1 r ocset1 vin1 = vin c ocset1 c boot1 q 1 q 2 c in1 l 1 vout2 c out2 r ocset2 vin2 = vin c ocset2 c boot2 q 3 q 4 c in2 l 2 vcc vin ISL6446A 80 82 84 86 88 90 92 94 96 98 100 0 5 10 15 20 25 load current (a) efficiency (%) v out = 5v v out = 3.3v november 6, 2012 fn8384.1
ISL6446A 2 fn8384.1 november 6, 2012 pin configuration ISL6446A (24 ld qsop) top viewi pin descriptions symbol pin # description boot1, 2 23, 14 these pins power the upper mosfet drivers of each pwm converter. the anode of each internal bootstrap diode is co nnected to the vcc pin. the cathode of the bootstrap diode is connected to this pin, which should also connect to the bootstrap capacit or. ugate1, 2 22, 15 these pins provide the gate drive for upper mosfets, bootstrapped from the vcc pin. phase1, 2 21, 16 these are the junction points of the upper mosfet sources, output filt er inductor and lower mosfet drains. conne ct these pins accordingly to the respective converter. lgate1, 2 20, 17 these are the outputs of the lower n-channel mosfet drivers, sourced from the vcc pin. pgnd 18 this pin provides the power ground connection for the lower gate drivers. this pin should be connected to the source of t he lower mosfet for pwm1 and pwm2 and the negative terminals of the external input capacitors. fb1, 2 4, 9 these pins are connected to the feedback resistor divider and provide the voltage feedback signals for the respective controller. they set the output voltage of the converter. in addition, the pgood circuit and ovp circuit use these inputs to monitor the output voltage status. comp1, 2 3, 10 these pins are the error amplifier outputs for the re spective pwm. they are used, along with the fb pins, as the c ompensation point for the pwm error amplifier. pgood 13 this is an open drain logic output used to indicate the st atus of the output voltages. this pin is pulled low when eithe r of the two pwm outputs is not within 10% of the respective nominal voltage or when the linear output drops below 75% of its nominal voltag e. to maintain the pgood function if the linear output is not used, connect lcfb to vcc. sgnd 6 this is the signal ground, common to both controllers, and mu st be routed separately from the high current grounds (pgnd). all voltage levels are measured with respect to this pin. vin 24 this pin powers the controllers with an internal linear regulator (if v in > 5.5v) and must be closely decoupled to ground using a ceramic capacitor as close to the vin pin as possible. v in is also the input voltage applied to the upper fet of both converters. vcc 19 this pin supplies the bias for the regulators, powers the low-side gate drivers and external boot circuitry for high-side gate drivers. the ic may be powered directly from a single 5v (10%) supply at this pin; when used as a 5v supply input, this pin must be externally connected to vin. when v in > 5.5, vcc is the output of the internal 5v linear regulator output. the vcc pin must always be decoupled to power ground with a minimum of 1f ceramic capacitor, placed very close to the pin. ocset1 ss1/en1 comp1 fb1 rt sgnd lcdr lcfb fb2 comp2 ss2/en2 ocset2 vin ugate1 phase1 lgate1 vcc lgate2 ugate2 boot2 pgood boot1 pgnd phase2 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 table 1. input supply configuration input pin configuration 5.5v to 24v connect the input supply to the vin pin. the vcc pin will provide a 5v output from the internal voltage regulator. 5v 10% connect the input supply to the vcc pin.
ISL6446A 3 fn8384.1 november 6, 2012 rt 5 this is the operating frequency adjustment pin. by placing a resistor from this pin to sgnd, the oscillator frequency can be programmed from 100khz to 2.5mhz. ss1/en1 ss2/en2 2, 11 these pins provide enable/disable and soft-start function for their respective controllers. the output is held off when th e pin is pulled to ground. when the chip is enabled, the regulated 30a pull-up current source charges the capacitor connected from the pin to ground. the output voltage of the converter follows the ramping voltage on the ss/en pin. see ?soft-start and voltage tracking? on page 12 for more details. lcfb 8 this pin is the feedback pin for the linear controller. an ex ternal voltage divider network connected to this pin sets the output voltage of the linear controller. if the linear controller is not used, tie this pin to vcc. lcdr 7 open drain output pnp transistor or p channel mosfet driver. lcdr connects to the base of an external pnp pass transistor or the gate of the mosfet to form a positive linear regulator. a sm all resistor can be inserted between the lcdr and the base of the pnp pass transistor or the gate of the mosfet to alleviate thermal stress at output short condition. ocset1, 2 1, 12 these pins are the overcu rrent set points for the respective pw m controllers. connect a resistor (r ocset ) from this pin to the drain of the upper mosfet. r ocset , an internal 110a current source, and the upper mosfet on-resistance r ds(on) set the converter overcurrent (oc) trip point according to equation 1: i oc includes the dc load current, as well as the ripp le current. an overcurrent trip initiates hiccup mode. the voltage on the ocset pin should not exceed 0.7v above the vin pin voltage for proper current sensing when the ugate is turned on. pin descriptions (continued) symbol pin # description i oc i ocset r ocset ? r ds on () --------------------------------------------------- = (eq. 1) ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL6446Aiaz isl6446 aiaz -40 to +85 24 ld qsop m24.15 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL6446A . for more information on msl please see tech brief tb363 .
ISL6446A 4 fn8384.1 november 6, 2012 block diagram pg3 lcfb fault3 figure 3. block diagram output1 drivers gate control logic dead-time control power on reset and control vcc ocset1 ugate1 lgate1 ss1/en1 ocset2 ugate2 lgate2 ss2/en2 fb2 comp2 fb1 clock and sawtooth generator lcfb lcdr pgnd sgnd reference comp1 rt 0.6v vcc vin 0.6v 0.6v pgood uvp1 ovp1 pg1 bias current 5v linear regulator boot1 phase1 vcc overcurrent output2 drivers gate control logic dead-time control vcc overcurrent boot2 phase2 pwm1 pwm2 0.6v 110a 110a pg1 pg2 pg3 en1 fault1 uvp2 ovp2 pg2 en2 fault2 vcc5 30a 100a 30a pgnd pgnd ss2 ss1 ss1 startup ss2 ramp1 ramp2 0 180 vcc vcc vcc5 30a uvp1 ovp1 pg1 en1 uvp2 ovp2 pg2 en2 en1 en2 g m *v e
ISL6446A 5 fn8384.1 november 6, 2012 typical application schematics boot1 ugate1 lcdr lcfb comp1 fb1 sgnd lgate1 pgnd vin1 = vin boot2 ugate2 lgate2 vin vcc vin ss1/en1 ss2/en2 pgood rt vout2 vout1 vin3 vcc vout1 vcc vout2 fb2 comp2 ISL6446A vin2 = vin connection voltage inputs required vin (4.5v to 24v) = vin1 = vin2 vcc (5v; internal if vin > 5.6v) vin3 ( vcc) for linear vout3 ocset1 phase1 ocset2 phase2 type-3 compensation shown type-3 compensation shown optional figure 4. ISL6446A typical application r 202 r 200 r 201 r 100 r 103 r 102 r 101 r 203 r ocset2 r ocset1 c 101 c 102 c 103 c 201 c 202 c 203 c vin c vcc c ocset2 c ocset1 c boot1 r 303 r rt r pgood c in3 c ss2/en2 c ss1/en1 r 302 r 300 r 301 c out3 l 100 c 301 c in2 c in1 c out2 c out1 q 101 q 102 q 201 q 202 q 301 l 200 c boot2 (for vin = vcc = 5v) r 304 0.9h 0.9h 2x680f/18m 2x100f 1x47f 2x680f/18m 2x100f
ISL6446A 6 fn8384.1 november 6, 2012 absolute maximum ratings (note 4) thermal information vcc to sgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.0v pgood to sgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to (vcc + 0.3v) ss1/en1, ss1/en2 to sgnd . . . . . . . . . . . . . . . . . . . .-0.3v to (vcc + 0.3v) comp1, comp2 to sgnd . . . . . . . . . . . . . . . . . . . . . . .-0.3v to (vcc + 0.3v) fb1, fb2, rt to sgnd . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to (vcc + 0.3v) lcdr, lcfb to sgnd . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to (vcc + 0.3v) vin, ocset1, and ocset2 to pgnd. . . . . . . . . . . . . . . . . . . . . -0.3v to +28v boot1 and boot2 to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot1 to phase1, and boot2 to phase2. . . . . . . . . . . . . . -0.3v to +6.0v ugate1 to phase1 . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (boot1 + 0.3v) ugate2 to phase2 . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (boot2 + 0.3v) lgate1, lgate2 to pgnd . . . . . . . . . . . . . . . . . . . . . . .-0.3v to (vcc + 0.3v) phase1, phase2 to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +28v sgnd to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . 2500v machine model (tested per jesd22-115-a) . . . . . . . . . . . . . . . . . . . 100v latch up (tested per jedec-78b leve l ii class a) . . . . 100ma @ +85c thermal resistance (typical) ja (c/w) jc (c/w) qsop package (notes 5, 6). . . . . . . . . . . . . 75 36 maximum junction temperature (plastic package) . . . .-55c to +150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% v in supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v to 24v ocset1 and ocset2 to vin . . . . . . . . . . . . . . . . . . . . . . . . . . -1.4v to +1.4v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. all voltages are measured with respect to gnd. 5. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. for jc , the ?case temp? location is taken at the package top center. electrical specifications operating conditions unless otherwise noted: v in = 12v, or v cc = 5v 10%, t a = -40c to +85c. typical values are at +25c. boldface limits apply over the operating temperature range, -40c to +85c parameter symbol test conditions min (note 9) typ max (note 9) units vin supply input operating supply current i cc_op v in = 5.5v or 12v; lgate x , ugate x open, fb forced above regulation point (no switching) 4.5 7.5 ma input standby supply current i cc_sb v in = 5.5v, 12v, 24v; ss1/en1 = ss2/en2 = 0v 1.25 3 ma vcc internal regulator output voltage v vcc v in = 5.6v, ss1/en1 = ss2/en2 = 0v no additional load 4.5 5.35 v output voltage v vcc v in = 24v, ss1/en1 = ss2/en2 = 0v no additional load 5.36 5.6 v output voltage v vcc v in = 12v, ss1/en1 = ss2/en2 = 0v ivcc= 80ma 4.5 5.2 v vcc current limit (note 7) i icc_cl vcc is pulled to pgnd; (note 8) 300 ma reference and soft-start reference voltage at fb1, fb2 v ref1 , v ref2 v in = 5v or 12v; t a = +25c 0.6000 v v in = 5v or 12v; t a = 0c to +85c 0.5925 0.6085 v v in = 5v or 12v; t a = -40c to +85c 0.5900 0.6085 v reference voltage at fb1, fb2 v ref1 , v ref2 v in = 24v; t a = +25c 0.6015 v v in = 24v; t a = 0c to +85c 0.5930 0.6100 v v in = 24v; t a = -40c to +85c 0.5915 0.6100 v en x /ss x soft-start current i ssx 20 30 40 a en x /ss x enable threshold v enx 850 940 1050 mv
ISL6446A 7 fn8384.1 november 6, 2012 en x /ss x enable threshold hysteresis v enx_hys (note 7) 15 mv en x /ss x soft-start top of ramp voltage v ssx_top (note 7) 3.12 v power-on reset on vcc rising threshold v por_r 4.2 4.4 4.48 v falling threshold v por_f 3.85 4.0 4.1 v pwm converters minimum ugate on time t ugate_min (note 7) 100 ns maximum duty cycle dc max v in = 5.0v or 12v; f sw = 300khz 95 % maximum duty cycle dc max v in = 5.0v; f sw = 2.58mhz 79 % fb x pin bias current i fbx vfb1 = vfb2 = 600mv -250 30 250 na oscillator low end frequency f sw v in = 12v; rt = 163k ? 103 khz oscillation frequency f sw v in = 5v or 12v; rt = 52.3k ? 270 300 330 khz v in = 24v; rt = 52.3k ? 270 305 340 khz high end frequency f sw v in = 5v; rt = 4.75k ? 2.20 2.5 2.85 mhz v in = 12v; rt = 4.75k ? 2.20 2.59 2.95 mhz frequency adjustment range f sw rt = 163k ? ; (note 7) 0.1 mhz rt = 4.75k ? ; (note 7) 2.6 mhz pwm sawtooth ramp amplitude (peak-to-peak) v p-p (note 8) 1.25 v pwm sawtooth ramp offset v pwm_off (note 8) 1.25 v pwm controller gate drivers (note 7) upper gate pull-up resistance 2.6 ? upper gate pull-down resistance 2 ? lower gate pull-up resistance 2.6 ? upper gate pull-down resistance 2 ? rise time c l = 3300pf 25 ns fall time c l = 3300pf 25 ns dead time between drivers 20 ns error amplifiers dc gain gain (note 8) 88 db gain-bandwidth product gbwp (note 8) 15 mhz slew rate sr (note 8); comp = 10pf 5 v/s maximum output voltage v ea_h i comp_src = 400a 3.9 4.2 v minimum output voltage v ea_l i comp_sink = 400a 0.8 1.1 v protection and output monitor overvoltage threshold ov 111 116 121 % undervoltage threshold uv 77 82 88 % electrical specifications operating conditions unless otherwise noted: v in = 12v, or v cc = 5v 10%, t a = -40c to +85c. typical values are at +25c. boldface limits apply over the operating temperature range, -40c to +85c (continued) parameter symbol test conditions min (note 9) typ max (note 9) units
ISL6446A 8 fn8384.1 november 6, 2012 ocset current source i ocset v ocset = 4.5v, t a = -40c 80 a ocset current source i ocset v ocset = 4.5v,t a = 25c 110 a ocset current source i ocset v ocset = 4.5v,t a = +85c 140 a linear controller drive sink current i lcdr lcdr 50 ma lcfb feedback threshold v lcfb t a = +25c 0.595 v t a = -40c to +85c 0.570 0.620 v t a = 0c to +70c 0.580 0.610 v lcfb input leakage current i lcfb (note 7) 80 na error amplifier transconductance gm (note 7); v lcfb = 0.6v, i lcdr = 21ma 2 a/v pgood power-good lower threshold pg_low x lcfb = vcc, ldo disabled pgood for ch1 and ch2 only 88 93 97 % power-good higher threshold pg_hi x lcfb = vcc, ldo disabled pgood for ch1 and ch2 only 105 110 115 % power-good lower threshold pg_low 3 ldo enabled, pgood for ldo; ch1 and ch2 disabled; (note 7) 72 % pgood delay t pgood (note 7); f sw = 1.4mhz 46 ms pgood leakage current i pgood v pullup = 5.5v 5 a pgood voltage low v pg_low i pgood = -4ma 0.5 v thermal shutdown temperature (note 8) 150 c shutdown hysteresis (note 8) 20 c notes: 7. limits established by characterization. 8. design guideline only; not production tested. 9. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications operating conditions unless otherwise noted: v in = 12v, or v cc = 5v 10%, t a = -40c to +85c. typical values are at +25c. boldface limits apply over the operating temperature range, -40c to +85c (continued) parameter symbol test conditions min (note 9) typ max (note 9) units
ISL6446A 9 fn8384.1 november 6, 2012 typical performance curves oscilloscope plots are taken using the ISL6446Aeval1z evaluation board, v in = 12v, v out1 = 5v, v out2 = 3.3v, f s = 300khz, unless otherwise noted. figure 5. output ripple (pwm1) figure 6. output ripple (pwm2) figure 7. load transient figure 8. pwm interleaving figure 9. pwm interleaving v out1 /ac phase 1 48mv p-p v out2 /ac phase 2 43mv p-p v in = 12v v out = 5v i out = 5a~15a v out1 /ac i step 1a/50mv i l1 phase 1 phase 2 v in = 12v v out1 = 5v v out2 = 3.3v i out1 = 0a i out2 = 0a phase 1 phase 2 v in = 12v v out1 = 5v v out2 = 3.3v i out1 = 25a i out2 = 25a
ISL6446A 10 fn8384.1 november 6, 2012 figure 10. en/ss start-up figure 11. en/ss start-up figure 12. en/ss shut-down figure 13. en/ss shut-down figure 14. pre-biased start-up (v out pre-biased at 3.5v) figur e 15. overcurrent protection typical performance curves oscilloscope plots are taken using the ISL6446Aeval1z evaluation board, v in = 12v, v out1 = 5v, v out2 = 3.3v, f s = 300khz, unless otherwise noted. (continued) v in = 12v v out1 = 5v v out2 = 3.3v i out1 = 0a i out2 = 0a en/ssx tied together en/ssx v out2 v out1 v in = 12v v out1 = 5v v out2 = 3.3v i out1 = 25a i out2 = 25a en/ssx tied together en/ssx v out2 v out1 v in = 12v v out1 = 5v v out2 = 3.3v i out1 = 0a i out2 = 0a en/ssx v out2 v out1 v in = 12v v out1 = 5v v out2 = 3.3v i out1 = 25a i out2 = 25a en/ssx v out2 v out1 v in = 12v v out1 = 5v i out = 0a en/ssx lgate phase v out en/ss v out phase i l v in = 12v v out1 = 5v i out = 10a~20a
ISL6446A 11 fn8384.1 november 6, 2012 figure 16. start-up with oc figure 17. overvoltage protection typical performance curves oscilloscope plots are taken using the ISL6446Aeval1z evaluation board, v in = 12v, v out1 = 5v, v out2 = 3.3v, f s = 300khz, unless otherwise noted. (continued) v in = 12v v out1 = 5v i out = s/c en/ssx v out phase i l v in = 12v v out1 = 5v i out = 10, fb = 1v en/ssx v out phase i l
ISL6446A 12 fn8384.1 november 6, 2012 functional description soft-start and voltage tracking after the vcc pin exceeds its rising por trip point (nominal 4.4v), the chip operation begins. both 30a current sources will start charging up the soft-starting capacitors respectively. the charging continues until the voltage across the soft-start capacitor reaches about 3.2v. from 1.0v to 1.6v, the outputs will ramp individually from zero to full-scale. now, if v = 0.6v, c = 0.1f, and i = 30a, then t = 2ms. figure 18 shows the typical waveforms for ss2/en2 and v out2 ; ss1/en1 and v out1 are similar. the soft-start ramps for each output can be selected independently. the basic timing equation is shown in equation 2: where: t is the charge time c is the external capacitance dv is the voltage charged i is the charging current (nominal 30a) finally, there is a delay after 1.6v, until the ramp gets to ~3.2v, which signals that the ramp is done; when both ramps are done, the pgood delay begins. to guarantee the soft-start is completed, please make sure the en/ssx pin voltage is able to reach above 3.2v at normal operation. figure 20 shows pre-biased output s before soft-start. the solid blue curve shows no pre-bias; th e output starts ramping from gnd. the magenta dotted line shows the output pre-biased to a voltage less than the final output. the fets don?t turn on until the soft-start ramp voltage exceeds the output voltage; then the output starts ramping seamlessly from there. the cyan dotted line shows the output pre-biased above the final output (but below the ovp (overvoltage protection)). the fets will not turn on until the end of the soft-start ramp; then the output will be quickly pulled down to the final value. if the output is pre-biased abov e the ovp level, the ISL6446A will go into ovp at the end of soft-sta rt, which will keep the fets off. see ?protection mechanisms? on page 14 for more details. vout1 has the same functionality as previously described for vout2. each output should react independently of the other, unless they are related by the circuit configuration. the linear output does not have a soft-start ramp; however, it may follow the ramp of its input supply, if timed to coincide with its rise, after the vcc rising por tr ip. if the input to the linear is from one of the two switcher outputs, then it will share the same ramp rate as the switcher. figure 18. soft-start v out2 (2v/div) gnd> gnd> ss2/en2 (0.5v/div) 1.0v 1.6v tc dv i ------- ? = (eq. 2) figure 19. voltage tracking 1.6v 1.0v gnd> v out2 (1v/div) gnd> gnd> gnd> v out (1v/div) ss2/en2 (0.5v/div) ss1/en1 (0.5v/div) figure 20. soft-start with pre-bias v out2 (2v/div) gnd> gnd> ss2/en2 (0.5v/div) v out2 pre-biased v out2 over-charged
ISL6446A 13 fn8384.1 november 6, 2012 pgood a group of comparators (separate from the protection comparators) monitor the output voltages (via the fb pins) for pgood. each switcher has a lower and upper boundary (nominally around 90% and 110% of the target value) and the linear has a lower boundary (around 75% of the target). once both switcher output ramps are done, and all 3 outputs are within their expected ranges, the pgood will start an internal timer, with equation 3: where: t pgood is the delay time (in sec) f sw is the switching frequency (in mhz) once the time-out is complete, the internal pull-down device will shut off, allowing the open-drain pgood output to rise through an external pull-up resistor, to a 5v (or lower) supply, which signals that the ?power is good?. figure 21 shows the three outputs turning on, and the delay for pgood. if any of the conditions is subsequently violated, then pgood goes low. once the voltage returns to the normal region, a new delay will start, after which the pgood will go high again. the pgood delay is inversely propor tional to the clock frequency. if the clock is running as slow as 524khz, the delay will be 125ms long. there is no way to adjust the pgood delay independently of the clock. switching frequency the switching frequency of the ISL6446A is determined by the external resistor placed from the rt pin to sgnd. see figure 22 for a graph of frequency vs rt resistance. use equation 4 to calculate the approximate rt resistor value for the desired switching frequency. the typical resistance for 100khz operation is 163k ? . running at both high frequency and high v in voltages is not recommended, due to the increased power dissipation on-chip (mostly from the internal vcc regulator, which supplies gate drivers). the user should check the maximum acceptable ic temperature, based on their particular conditions. output regulation figure 23 shows the gene ric feedback resistor circuit for any of the two pwm v out ?s; the v out is divided down to equal the reference. all three use a 0.6v internal reference (check the ?electrical specifications? table on page 6 for the exact reference value at 24v). the r up is connected to the v out ; the r low to gnd; the common point goes to the fb pin. v out must be greater than 0.6v and 2 resistors are needed, and their accuracy directly affect the regulator tolerance. use equation 6 to choose the resistor values. r up is part of the compensation network for the swit chers, and should be selected to be compatible; 1k ? to 5k ? is a good starting value. find fb from the ?electrical specifications? table on page 7 (for the right condition), plug in the desired value for v out , and solve for r low . the maximum duty cycle of the ISL6446A approaches 100% at low frequency, but falls off at higher frequency; see the ?electrical specifications? table on page 7. in addition, there is a minimum ugate pulse width, in order to properly sense overcurrent. the two switchers are 180 out of phase. t pgood 0.065 f sw -------------- - = (eq. 3) figure 21. pgood delay gnd> v out1 (2v/div) v out2 (2v/div) gnd> gnd> gnd> v out3 (2v/div) pgood (5v/div) r t f sw 11290 ---------------- ?? ?? 1.093 ? = (eq. 4) figure 22. frequency vs r t resistor 100k 200k 500k 1m 2m switching frequency (hz) 3k 10k 50k 100k 300k 30k r t value ( ? ) figure 23. output regulation comp fb v out r low r up ea 0.6v fb v out r low r up r low + ----------------------------------- ? = (eq. 5) r low fb r up ? v out fb ? ----------------------------- - = (eq. 6)
ISL6446A 14 fn8384.1 november 6, 2012 linear regulator the linear regulator controller is a trans-conductance amplifier with a nominal gain of 2a/v. the n-channel mosfet output buffer can sink a minimum of 50ma. the reference voltage is 0.6v. with 0v differential at its input, the controller sinks 21ma of current. for better load regulation, it is recommended that the resistor from the ldo input to the base of the pnp (or gate of the pfet) is set so that the sink current at g4 pin is within 9ma to 31ma over the entire load and temperature range. an external pnp transistor or p-channel mosfet pass device can be used. the dominant pole for the loop can be placed at the base of the pnp (or gate of the pfet), as a capacitor from emitter-to-base (source to gate of a pfet). better load transient response is achieved however, if the dominant pole is placed at the output with a capacitor to ground at the output of the regulator. protection mechanisms ocp - (function independent for both pwm). the overcurrent function protects the pwm converter from a shorted output by using the upper mosfet?s on-resistance, r ds(on) to monitor the current. this method enhances the converter?s efficiency and reduces cost by eliminating a current sensing resistor. the overcurrent function latches off the outputs to provide fault protection. a resistor connected to the drain of the upper mosfet and ocset pin programs the overcurrent trip level. the phase node voltage will be compared against the voltage on the ocset pin, while the upper mosfet is on . a current (typically 110a) is pulled from the ocset pin to establish the ocset voltage. if phase is lower than ocset while th e upper mosfet is on then an overcurrent condition is detected for that clock cycle. the upper gate pulse is immediately terminated, and a counter is incremented. if an overcurrent condition is detected for 32 consecutive clock cycles, the ISL6446A output is latched off with gate drivers three-stated. the switcher will restart when the ss/en pin is externally driven below 1v, or if power is recycled to the chip. during soft-start, both pulse termination current limiting and the 32-cycle counter are enabled. uvp - (function independent for bo th pwm). if the voltage on the fb pin falls to 82% (typical) of the reference voltage for 8 consecutive pwm cycles, then the circuit enters into soft-start hiccup mode. during hiccup, the external capacitor on the ss/en pin is discharged, then released and a soft-start cycle is initiated. the uvp comparator is separate from the one sensing for pgood, which should have alread y detected a problem, before the uvp trips. ovp - (function independent for both pwm). ovp function is enabled after the soft start has finished. if voltage on the fb pin rises to 116% (typical) of the reference voltage, the lower gate driver is turned on continuous ly. if the overvoltage condition continues for 32 consecutive pwm cycles, then that output is latched off with the gate drivers three-stated. the capacitor on the ss/en pin will not be discharged. the switcher will restart when the ss/en pin is externally driven below 1v, or if power is recycled to the chip. the ovp comparator is separate from the one sensing for pgood, which should have already detected a problem, before the ovp trips. application guidelines pwm controller discussion the pwm must be compensated such that it achieves the desired transient performance goals, stability, and dc regulation requirements. the first parameter that needs to be chosen is the switching frequency, f sw . this decision is based on the overall size constraints and the frequency plan of the end equipment. smaller space requires higher frequency. this allows the output inductor, input capacitor bank, and output capacitor bank to be reduced in size and/or value. the power supply must be designed such that the frequency and it s distribution over component tolerance, time and temperature causes minimal interference in rf stages, if stages, pll loops, mixers, etc. inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the co nverter?s response time to the load transient. the inductor value determines the converter?s ripple current, and the ripple voltage is a function of the ripple current. the ripple current and voltage are approximated by the following equations, where esr is the output capacitance esr value. increasing the value of inductance reduces the ripple current and voltage. however, the large inductance value reduces the converter?s response time to a load transient (and usually increases the dcr of the inductor, which decreases the efficiency). increasing the switching frequency (f sw ) for a given inductor also reduces the ripple current and voltage. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fast control loop design, the ISL6446A will 0.59 0.6 0.62 0.63 0.65 0 40 60 feedback voltage (v) error amplifier sink 20 50 30 10 current (ma) 0.61 0.64 figure 24. linear controller gain i v in - v out f sw l ? ------------------------------- - v out v in --------------- - ? = (eq. 7) v out = i x esr (eq. 8)
ISL6446A 15 fn8384.1 november 6, 2012 provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transient current level. during this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor. mini mizing the resp onse time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. th e following equations give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. with a +5v input source, the worst case response time can be either at th e application or removal of load and dependent up on the output voltage setting. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. finally, check that the inductor i sat rating is sufficiently above the maximum output current (dc load plus ripple current). output capacitor selection an output capacitor is required to filter the output and supply the load transient current. the filtering requirements are a function of the switching frequency and the ripple current. the load transient requirements are a functi on of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern microprocessors produce transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) an d voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit boar d wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. keep in mind that not all applications have the same requirements; some may need many ceramic capacitors in parallel; others may need only one. use only specialized low-esr capacitors intended for switching-regulator applications fo r the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor's esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfort unately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with freq uency to select a suitable component. in most cases, multip le electrolytic capacitors of small case size perform better th an a single large case capacitor. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q1 (upper fet) turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of q1 and the source of q2 (lower fet). the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25x greater than the maximum input vo ltage and a voltage rating of 1.5x is a conservative guideline. the rms current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the dc load current. switcher mosfet selection v in for the ISL6446A has a wi de operating voltage range allowed, so both fets should have a source-drain breakdown voltage (v ds ) above the maximum supply voltage expected; 20v or 30v are typical values available. the ISL6446A gate drivers (ugate x and lgate x ) were designed to drive single fets (for up to ~10a of load current) or smaller dual fets (up to 4a). both sets of driv ers are sourced by the internal vcc regulator (unless v in = v cc = 5v, in which case the gate driver current comes from the external 5v supply). the maximum current of the regulator (i cc_max) is listed in the ?electrical specifications? table on page 6; this may limit how big the fets can be. in addition, the power dissipation of the regulator is a major contributor to the overall ic power dissipa tion (especially as c in of the fet or v in or f sw increases). since v cc is around 5v, that affects the fet selection in two ways. first, the fet gate-source voltage rating (v gs ) can be as low as 12v (this rating is usually consistent with the 20v or 30v breakdown chosen above). second, the fets must have a low threshold voltage (around 1v), in order to have its r ds(on) rating at v gs = 4.5v in the 10m ? to 40m ? range that is typically used for these applications. while some fets are also rated with gate voltages as low as 2.7v, with typical thresholds under 1v, these can cause application problems. as lgate shuts off the lower fet, it does not take much ringing in the lgate signal to turn the lower fet back on, while the upper fet is starting to turn on, causing some shoot-through current. therefore, avoid fets with thresholds below 1v. if the power efficiency of the system is important, then other fet parameters are also considered. efficiency is a measure of power losses from input to output, and it contains two major components: losses in the ic (mostly in the gate drivers) and losses in the fets. for low duty cycle applications (such as 12v in to 1.5v out), the upper fet is usually chosen for low gate charge, since switching losses are key, while the lower fet is chosen for low r ds(on) , since it is on most of th e time. for high duty cycles (such as 5.0v in to 3.3v out), the opposite may be true. t rise l out i tran v in v out ? -------------------------------------- - = (eq. 9) t fall l out i tran v out -------------------------------------- - = (eq. 10)
ISL6446A 16 fn8384.1 november 6, 2012 feedback compensation equations this section highlights the design consideration for a voltage mode controller requiring external compensation. to address a broad range of applications, a type-3 feedback network is recommended (see figure 25). figure 26 highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable to the ISL6446A circuit. the output voltage (v out ) is regulated to the reference voltage, v ref . the error amplifier output (comp pin voltage) is compared with the oscillator (osc) modified sawtooth wave to provide a pulse-width modulated wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l and c). the output filter capacitor bank?s equivalent series resistance is represen ted by the series resistor e. the modulator transfer function is the small-signal transfer function of v out /v comp . this function is dominated by a dc gain, given by d max v in /v osc , and shaped by the output filter, with a double pole break frequency at f lc and a zero at f ce . for the purpose of this analysis, l and d represent the channel inductance and its dcr, while c and e represent the total output capacitance and its equivalent series resistance. the compensation network consists of the error amplifier (internal to the ISL6446A) and the external r1 to r3, c1 to c3 components. the goal of the compensation network is to provide a closed loop transfer function with high 0db crossing frequency (f 0 ; typically 0.1 to 0.3 of f sw ) and adequate phase margin (better than 45). phase margin is the difference between the closed loop phase at f 0db and 180. the equations that follow relate the compensation network? s poles, zeros and gain to the components (r1 , r2, r3, c1 , c2, and c3) in figure 26. use the following guidelines for locating the poles and zeros of the compensation network: 1. select a value for r1 (1k ? to 5k ? , typically). calculate the value for r2 for desired converter bandwidth (f 0 ). if setting the output voltage via an offset resistor connected to the fb pin, ro in figure 26, the design procedure can be followed as presented in equation 13. figure 25. compensation configuration for ISL6446A circuit ISL6446A comp c1 r2 r1 fb v out c2 r3 c3 figure 26. voltage-mode buck converter compensation design - + e/a vref comp c1 r2 r1 fb c2 r3 c3 l c v in pwm circuit half-bridge drive oscillator e external circuit ISL6446A v out v osc d ugate lgate ro phase f lc 1 2 lc ? ? --------------------------- = (eq. 11) f ce 1 2 ce ?? ----------------------- - = (eq. 12) r2 v osc r1 f 0 ?? d max v in f lc ?? --------------------------------------------- = (eq. 13)
ISL6446A 17 fn8384.1 november 6, 2012 2. calculate c1 such that f z1 is placed at a fraction of the f lc , at 0.1 to 0.75 of f lc (to adjust, change the 0.5 factor to desired number). the higher the quality factor of the output filter and/or the higher the ratio f ce /f lc , the lower the f z1 frequency (to maximize phase boost at f lc ). 3. calculate c2 such that f p1 is placed at f ce . 4. calculate r3 such that f z2 is placed at f lc . calculate c3 such that f p2 is placed below f sw (typically, 0.5 to 1.0 times f sw ). f sw represents the switching frequency. change the numerical factor to reflect desired placement of this pole. placement of f p2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the hf ripple component at the comp pin and minimizing resultant duty cycle jitter. it is recommended a mathematical model is used to plot the loop response. check the loop ga in against the error amplifier?s open-loop gain. verify phase margin results and adjust as necessary. the following equations describe the frequency response of the modulator (g mod ), feedback compensation (g fb ) and closed-loop response (g cl ): where: compensation break frequency equations figure 27 shows an asymptotic plot of the dc/dc converter?s gain vs frequency. the actual modulator gain has a high gain peak dependent on the quality factor (q) of the output filter, which is not shown. using the previously ment ioned guidelines should yield a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the co mpensation gain. check the compensation gain at f p2 against the capabilities of the error amplifier. the closed loop gain, g cl , is constructed on the log-log graph of figure 27 by adding the modulator gain, g mod (in db), to the feedback compensation gain, g fb (in db). this is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. a stable control loop has a gain crossing with close to a -20db/decade slope and a phas e margin greater than 45. include worst case component variations when determining phase margin. the mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. when designing co mpensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, f sw . layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close together as possible using ground plane construction or sing le point grounding. figure 28 shows the critical power components of the converter. to minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. the components shown in figure 28 should be located as close together as possible. please note that the capacitors c in and c out each represent numerous physical capacitors. locate the ISL6446A within 1 inch of the mosfets, q1 and q2. the circuit traces for the mosfets? gate and source connections from the ISL6446A must be sized to handle up to 2a peak current. c1 1 2 r2 0.5 f lc ??? ----------------------------------------------- - = (eq. 14) c2 c1 2 r2 c1 f ce 1 ? ??? --------------------------------------------------------- = (eq. 15) r3 r1 f sw f lc ------------ 1 ? --------------------- - = c3 1 2 r3 0.7 f sw ??? ------------------------------------------------- = (eq. 16) g mod f () d max v in ? v osc ----------------------------- - 1sf () ec ?? + 1sf () ed + () c ?? s 2 f () lc ?? ++ ---------------------------------------------------------------------------------------- ? = (eq. 17) g fb f () 1sf () r2 c1 ?? + sf () r1 c1 c2 + () ?? ------------------------------------------------------ ? = 1sf () r1 r3 + () c3 ?? + 1sf () r3 c3 ?? + () 1sf () r2 c1 c2 ? c1 c2 + ---------------------- ?? ?? ?? + ?? ?? ? ---------------------------------------------------------------------------------------------------------------------------- - ? (eq. 18) g cl f () g mod f () g fb f () ? = (eq. 19) sf () 2 fj ?? = f z1 1 2 r2 c1 ?? ------------------------------- - = (eq. 20) f z2 1 2 r1 r3 + () c3 ?? --------------------------------------------------- = (eq. 21) f p1 1 2 r2 c1 c2 ? c1 c2 + ---------------------- ?? ---------------------------------------------- - = (eq. 22) f p2 1 2 r3 c3 ?? ------------------------------- - = (eq. 23) 0 f p1 f z2 open loop e/a gain f z1 f p2 f lc f ce compensation gain gain frequency modulator gain figure 27. asymptotic bode plot of converter gain closed loop gain 20 d max v ? in v osc ----------------------------- - log 20 r2 r1 ------- - ?? ?? log log log f 0 g mod g fb g cl
ISL6446A 18 fn8384.1 november 6, 2012 figure 29 shows the circuit traces that require additional layout consideration. use single point an d ground plane construction for the circuits shown. locate the rt resistor as close as possible to the rt pin and the sgnd pin. provide local decoupling between vcc and gnd pins. for each switcher, minimize an y leakage current paths on the ss/en pin and locate the capacitor, c ss close to the ss/en pin because the internal current source is only 30a. all of the compensation network components for each switcher should be located near the associated co mp and fb pins. locate the capacitor, c boot as close as practical to the boot and phase pins (but keep the noisy phase plane away from the ic (except for the phase pin connection). the ocset circuits (see figure 4 on page 5) should have a separate trace from the upper fet to the ocset r and c; that will more accurately sense the vin at the fet than just tying them to the vin plane. the ocset r and c should be placed near the ic pins. figure 28. printed circuit board power and ground planes or islands pgnd l out c out lgate ugate q1 q2 v in v out return ISL6446A c in load phase figure 29. printed circuit board power and ground planes or islands +v in ISL6446A ss sgnd vin boot l out c out v out load q1 q2 +v in c boot c vin c ss pgnd vcc c vcc c in rt r rt sgnd pgnd phase
ISL6446A 19 fn8384.1 november 6, 2012 products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: ISL6446A to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change november 6, 2012 fn8384.1 initial release.
ISL6446A 20 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8384.1 november 6, 2012 for additional products, see www.intersil.com/product_tree package outline drawing shrink small outline plastic packages (ssop) quarter size outline plastic packages (qsop) notes: 1. symbols are defined in the ?mo seri es symbol list? in section 2.2 of publication number 95. 2. dimensioning and tole rancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimen- sion at maximum material condition. 10. controlling dimension: inches. converted millimeter dimensions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m24.15 24 lead shrink small outline plastic package (0.150? wide body) symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - a2 - 0.061 -1.54- b 0.008 0.012 0.20 0.30 9 c 0.007 0.010 0.18 0.25 - d 0.337 0.344 8.55 8.74 3 e 0.150 0.157 3.81 3.98 4 e 0.025 bsc 0.635 bsc - h 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 l 0.016 0.050 0.41 1.27 6 n24 247 0 8 0 8 - rev. 2 6/04

▲Up To Search▲

Price & Availability of ISL6446A

	To Download ISL6446A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .